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libbladeRF
1.7.2
Nuand bladeRF library
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In a most cases, higher-level routines should be used. These routines are only intended to support development and testing.
Use these routines with great care, and be sure to reference the relevant schematics, data sheets, and source code (i.e., firmware and hdl).
Be careful when mixing these calls with higher-level routines that manipulate the same registers/settings.
These functions are thread-safe.
Data Structures | |
struct | bladerf_lms_dc_cals |
Macros | |
#define | BLADERF_GPIO_LMS_RX_ENABLE (1 << 1) |
#define | BLADERF_GPIO_LMS_TX_ENABLE (1 << 2) |
#define | BLADERF_GPIO_TX_LB_ENABLE (2 << 3) |
#define | BLADERF_GPIO_TX_HB_ENABLE (1 << 3) |
#define | BLADERF_GPIO_COUNTER_ENABLE (1 << 9) |
#define | BLADERF_GPIO_RX_MUX_MASK (0x7 << BLADERF_GPIO_RX_MUX_SHIFT) |
#define | BLADERF_GPIO_RX_MUX_SHIFT 8 |
#define | BLADERF_GPIO_RX_LB_ENABLE (2 << 5) |
#define | BLADERF_GPIO_RX_HB_ENABLE (1 << 5) |
#define | BLADERF_GPIO_FEATURE_SMALL_DMA_XFER (1 << 7) |
#define | BLADERF_GPIO_TIMESTAMP (1 << 16) |
#define | BLADERF_GPIO_TIMESTAMP_DIV2 (1 << 17) |
#define | BLADERF_TRIGGER_REG_ARM ((uint8_t) (1 << 0)) |
#define | BLADERF_TRIGGER_REG_FIRE ((uint8_t) (1 << 1)) |
#define | BLADERF_TRIGGER_REG_MASTER ((uint8_t) (1 << 2)) |
#define | BLADERF_TRIGGER_REG_LINE ((uint8_t) (1 << 3)) |
Functions | |
API_EXPORT int CALL_CONV | bladerf_si5338_read (struct bladerf *dev, uint8_t address, uint8_t *val) |
API_EXPORT int CALL_CONV | bladerf_si5338_write (struct bladerf *dev, uint8_t address, uint8_t val) |
API_EXPORT int CALL_CONV | bladerf_lms_read (struct bladerf *dev, uint8_t address, uint8_t *val) |
API_EXPORT int CALL_CONV | bladerf_lms_write (struct bladerf *dev, uint8_t address, uint8_t val) |
API_EXPORT int CALL_CONV | bladerf_lms_set_dc_cals (struct bladerf *dev, const struct bladerf_lms_dc_cals *dc_cals) |
API_EXPORT int CALL_CONV | bladerf_lms_get_dc_cals (struct bladerf *dev, struct bladerf_lms_dc_cals *dc_cals) |
API_EXPORT int CALL_CONV | bladerf_config_gpio_read (struct bladerf *dev, uint32_t *val) |
API_EXPORT int CALL_CONV | bladerf_config_gpio_write (struct bladerf *dev, uint32_t val) |
API_EXPORT int CALL_CONV | bladerf_xb_spi_write (struct bladerf *dev, uint32_t val) |
API_EXPORT int CALL_CONV | bladerf_calibrate_dc (struct bladerf *dev, bladerf_cal_module module) |
API_EXPORT int CALL_CONV | bladerf_read_trigger (struct bladerf *dev, bladerf_module module, bladerf_trigger_signal signal, uint8_t *val) |
API_EXPORT int CALL_CONV | bladerf_write_trigger (struct bladerf *dev, bladerf_module module, bladerf_trigger_signal signal, uint8_t val) |
#define BLADERF_GPIO_COUNTER_ENABLE (1 << 9) |
Counter mode enable
Setting this bit to 1 instructs the FPGA to replace the (I, Q) pair in sample data with an incrementing, little-endian, 32-bit counter value. A 0 in bit specifies that sample data should be sent (as normally done).
This feature is useful when debugging issues involving dropped samples.
Definition at line 4001 of file libbladeRF.h.
#define BLADERF_GPIO_FEATURE_SMALL_DMA_XFER (1 << 7) |
This GPIO bit configures the FPGA to use smaller DMA transfers (256 cycles instead of 512). This is required when the device is not connected at Super Speed (i.e., when it is connected at High Speed).
However, the caller need not set this in bladerf_config_gpio_write() calls. The library will set this as needed; callers generally do not need to be concerned with setting/clearing this bit.
Definition at line 4040 of file libbladeRF.h.
#define BLADERF_GPIO_LMS_RX_ENABLE (1 << 1) |
Enable LMS receive
Definition at line 3969 of file libbladeRF.h.
#define BLADERF_GPIO_LMS_TX_ENABLE (1 << 2) |
Enable LMS transmit
Definition at line 3976 of file libbladeRF.h.
#define BLADERF_GPIO_RX_HB_ENABLE (1 << 5) |
Switch to use RX high band (1.5GHz - 3.8GHz)
Definition at line 4028 of file libbladeRF.h.
#define BLADERF_GPIO_RX_LB_ENABLE (2 << 5) |
Switch to use RX low band (300M - 1.5GHz)
Definition at line 4021 of file libbladeRF.h.
#define BLADERF_GPIO_RX_MUX_MASK (0x7 << BLADERF_GPIO_RX_MUX_SHIFT) |
Bit mask representing the rx mux selection
Definition at line 4009 of file libbladeRF.h.
#define BLADERF_GPIO_RX_MUX_SHIFT 8 |
Starting bit index of the RX mux values in FX3 <-> FPGA GPIO bank
Definition at line 4014 of file libbladeRF.h.
#define BLADERF_GPIO_TIMESTAMP (1 << 16) |
Enable-bit for timestamp counter in the FPGA
Definition at line 4045 of file libbladeRF.h.
#define BLADERF_GPIO_TIMESTAMP_DIV2 (1 << 17) |
Timestamp 2x divider control.
By default (value = 0), the sample counter is incremented with I and Q, yielding two counts per sample.
Set this bit to 1 to enable a 2x timestamp divider, effectively achieving 1 timestamp count per sample.
Definition at line 4063 of file libbladeRF.h.
#define BLADERF_GPIO_TX_HB_ENABLE (1 << 3) |
Switch to use TX high band (1.5GHz - 3.8GHz)
Definition at line 3990 of file libbladeRF.h.
#define BLADERF_GPIO_TX_LB_ENABLE (2 << 3) |
Switch to use TX low band (300MHz - 1.5GHz)
Definition at line 3983 of file libbladeRF.h.
#define BLADERF_TRIGGER_REG_ARM ((uint8_t) (1 << 0)) |
Trigger control register "Arm" bit
This bit arms (i.e., enables) the trigger controller when set to 1. Samples will be gated until the "Fire" bit has been asserted.
A 0 in this bit disables the trigger controller. Samples will continue to flow as they normally do in this state.
Definition at line 4122 of file libbladeRF.h.
#define BLADERF_TRIGGER_REG_FIRE ((uint8_t) (1 << 1)) |
Trigger control register "Fire" bit
For a master, this bit causes a trigger to be sent to all slave devices. Once this trigger is received (the master "receives" it immediately as well), devices begin streaming samples.
This bit has no effect on slave devices.
Definition at line 4133 of file libbladeRF.h.
#define BLADERF_TRIGGER_REG_LINE ((uint8_t) (1 << 3)) |
Trigger control registers "line" bit
This is a read-only register bit that denotes the current state of the the trigger signal.
Definition at line 4150 of file libbladeRF.h.
#define BLADERF_TRIGGER_REG_MASTER ((uint8_t) (1 << 2)) |
Trigger control register "Master" bit
Selects whether the device is a trigger master (1) or trigger slave (0). The trigger master drives the trigger signal as an output. Slave devices configure the trigger signal as an input.
Definition at line 4142 of file libbladeRF.h.
API_EXPORT int CALL_CONV bladerf_calibrate_dc | ( | struct bladerf * | dev, |
bladerf_cal_module | module | ||
) |
Perform DC calibration
dev | Device handle |
module | Module to calibrate |
API_EXPORT int CALL_CONV bladerf_config_gpio_read | ( | struct bladerf * | dev, |
uint32_t * | val | ||
) |
Read a configuration GPIO register
dev | Device handle |
val | Pointer to variable the data should be read into |
API_EXPORT int CALL_CONV bladerf_config_gpio_write | ( | struct bladerf * | dev, |
uint32_t | val | ||
) |
Write a configuration GPIO register. Callers should be sure to perform a read-modify-write sequence to avoid accidentally clearing other GPIO bits that may be set by the library internally.
dev | Device handle |
val | Data to write to GPIO register |
API_EXPORT int CALL_CONV bladerf_lms_get_dc_cals | ( | struct bladerf * | dev, |
struct bladerf_lms_dc_cals * | dc_cals | ||
) |
Retrieve the current DC calibration values from the LMS6002
[in] | dev | Device handle |
[out] | dc_cals | Populated with current values |
API_EXPORT int CALL_CONV bladerf_lms_read | ( | struct bladerf * | dev, |
uint8_t | address, | ||
uint8_t * | val | ||
) |
Read a LMS register
dev | Device handle |
address | LMS register offset |
val | Pointer to variable the data should be read into |
API_EXPORT int CALL_CONV bladerf_lms_set_dc_cals | ( | struct bladerf * | dev, |
const struct bladerf_lms_dc_cals * | dc_cals | ||
) |
Manually load values into LMS6002 DC calibration registers.
This is generally intended for applying a set of known values resulting from a previous run of the LMS autocalibrations.
dev | Device handle |
dc_cals | Calibration values to load. Values set to <0 will not be applied. |
API_EXPORT int CALL_CONV bladerf_lms_write | ( | struct bladerf * | dev, |
uint8_t | address, | ||
uint8_t | val | ||
) |
Write a LMS register
dev | Device handle |
address | LMS register offset |
val | Data to write to register |
API_EXPORT int CALL_CONV bladerf_read_trigger | ( | struct bladerf * | dev, |
bladerf_module | module, | ||
bladerf_trigger_signal | signal, | ||
uint8_t * | val | ||
) |
Read trigger control register
dev | Device handle |
module | Module to read from |
signal | Trigger signal (control register) to read from |
val | Pointer to variable that register is read into See the BLADERF_TRIGGER_REG_* macros for the meaning of each bit. |
API_EXPORT int CALL_CONV bladerf_si5338_read | ( | struct bladerf * | dev, |
uint8_t | address, | ||
uint8_t * | val | ||
) |
Read a Si5338 register
dev | Device handle |
address | Si5338 register offset |
val | Pointer to variable the data should be read into |
API_EXPORT int CALL_CONV bladerf_si5338_write | ( | struct bladerf * | dev, |
uint8_t | address, | ||
uint8_t | val | ||
) |
Write a Si5338 register
dev | Device handle |
address | Si5338 register offset |
val | Data to write to register |
API_EXPORT int CALL_CONV bladerf_write_trigger | ( | struct bladerf * | dev, |
bladerf_module | module, | ||
bladerf_trigger_signal | signal, | ||
uint8_t | val | ||
) |
Write trigger control register
dev | Device handle |
module | Module to configure |
signal | Trigger signal to configure |
val | Data to write into the trigger control register. See the BLADERF_TRIGGER_REG_* macros for options. |
API_EXPORT int CALL_CONV bladerf_xb_spi_write | ( | struct bladerf * | dev, |
uint32_t | val | ||
) |
Write value to secondary XB SPI
dev | Device handle |
val | Data to write to XB SPI |